circuit RegisterFile :
  module RegisterFile :
    input clock : Clock
    input reset : UInt<1>
    output io : { flip wen : UInt<1>, flip waddr : UInt<5>, flip wdata : UInt<32>, flip raddr : UInt<5>[4], rdata : UInt<32>[4]}

    wire _reg_WIRE : UInt<32>[32] @[RegisterFile.scala 15:28]
    _reg_WIRE[0] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[1] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[2] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[3] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[4] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[5] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[6] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[7] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[8] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[9] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[10] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[11] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[12] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[13] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[14] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[15] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[16] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[17] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[18] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[19] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[20] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[21] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[22] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[23] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[24] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[25] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[26] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[27] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[28] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[29] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[30] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    _reg_WIRE[31] <= UInt<32>("h0") @[RegisterFile.scala 15:28]
    reg reg : UInt<32>[32], clock with :
      reset => (reset, _reg_WIRE) @[RegisterFile.scala 15:20]
    when io.wen : @[RegisterFile.scala 17:17]
      reg[io.waddr] <= io.wdata @[RegisterFile.scala 18:19]
    node _T = eq(io.raddr[0], UInt<1>("h0")) @[RegisterFile.scala 21:23]
    when _T : @[RegisterFile.scala 21:32]
      io.rdata[0] <= UInt<1>("h0") @[RegisterFile.scala 22:19]
    else :
      io.rdata[0] <= reg[io.raddr[0]] @[RegisterFile.scala 24:19]
    node _T_1 = eq(io.raddr[1], UInt<1>("h0")) @[RegisterFile.scala 21:23]
    when _T_1 : @[RegisterFile.scala 21:32]
      io.rdata[1] <= UInt<1>("h0") @[RegisterFile.scala 22:19]
    else :
      io.rdata[1] <= reg[io.raddr[1]] @[RegisterFile.scala 24:19]
    node _T_2 = eq(io.raddr[2], UInt<1>("h0")) @[RegisterFile.scala 21:23]
    when _T_2 : @[RegisterFile.scala 21:32]
      io.rdata[2] <= UInt<1>("h0") @[RegisterFile.scala 22:19]
    else :
      io.rdata[2] <= reg[io.raddr[2]] @[RegisterFile.scala 24:19]
    node _T_3 = eq(io.raddr[3], UInt<1>("h0")) @[RegisterFile.scala 21:23]
    when _T_3 : @[RegisterFile.scala 21:32]
      io.rdata[3] <= UInt<1>("h0") @[RegisterFile.scala 22:19]
    else :
      io.rdata[3] <= reg[io.raddr[3]] @[RegisterFile.scala 24:19]

